When digital data signals that contain long runs of either ones or zeroes are sent over a long transmission line, the edges that correspond to the data transitions (either 0→1 or 1→0) become severely distorted by the bandwidth limitation and the frequency dispersion of the transmission line. This phenomenon, known as inter-symbol interference (ISI), moves the transition edges associated with these long runs from their ideal clock positions, thus interfering with the correct recovery of data by the receiver.
Data transmission system designers have taken a system approach to mitigate the problem of ISI by utilizing a technique referred to as “pre-emphasis” in the driver circuit. For example, the transmission line driver asserts a lower voltage level “1” that is less strong than a nominal “1” voltage level prior to transitioning to the “0” voltage level. In a similar manner, the transmission line driver asserts a higher voltage level “0” (compared to the nominal value) prior to transitioning to the “1” voltage level. These emphasized transitions tend to compensate for the anticipated distortion of the pulses that follow long high or long low bit sequences. In typical prior art arrangements, the emphasis is provided by sourcing current through a resistor to generate the drive voltage. As a result, a reduced current is driven for the 1→1 or 0→0 bit transitions, as compared to the level-shifting 1→0 or 0→1 bit transitions. While useful, this approach requires a relatively high power and is not suitable for low power applications, such as CMOS drivers.
Thus, a need remains in the art for an arrangement that addresses the ISI concerns of high speed CMOS transmission systems where pre-emphasis arrangements require too much power to be effective.